Two important objectives in the design and fabrication of logic circuits are to increase switching speed and reduce power dissipation. These objectives can be achieved through improved fabrication processes as well as through superior circuit designs. The development of a new fabrication process is extremely costly in terms of both time and expense. As a result, significant improvements in process technology come about rather slowly. In the interim, improvements in performance and power consumption are more likely to be achieved by modifying existing designs or developing new logic circuit designs.
One approach to decrease power dissipation in a logic circuit is to "recharacterize" an existing circuit to operate at a lower voltage, thereby reducing its power consumption. "Recharacterization" refers to taking an existing circuit and modifying it so that it operates at another voltage. There is a great demand in the semiconductor industry to recharacterize existing designs so that they operate effectively at lower voltages. If an existing design can be recharacterized without sacrificing performance, it can eliminate costly changes to the fabrication process or engineering time in redesigning the circuit. Unfortunately, present attempts to recharacterize existing circuits have failed because they have not produced the desired performance.
There is always a need for logic designs that reduce power consumption without sacrificing performance, but one type of design where the problem is particularly acute is pass gate logic. Pass gate logic to logic circuits where logical functions are implemented using a network of pass gates coupled in series. When complex logic functions are implemented using pass gate logic, there are often performance problems caused by the threshold voltage drops across pass gates in the design. As a result of the threshold voltage drop, the output of a pass gate may not be a valid logic signal. This problem is even worse for recharacterized circuits.
The easiest way to explain pass gate logic design and highlight the problems associated with it is through an example. FIG. 1 is simple schematic diagram of a CMOS inverter. The input voltage 20 to a typical gate such as the inverter in FIG. 1 is considered a valid logic signal if it is within 20 percent of the supply voltage 22. For 5 volt circuit designs, an input voltage between 4 and 5 volts is a valid logic high, while an input voltage between 1 and 0 volt is a valid logic low. For 3 volt designs, an input voltage between 2.4 and 3 volts is a valid logic high, while an input voltage between 0.6 and 0 volt is a valid logic low. When an input of a logic gate has a valid logic signal, then the output of that gate will have a minimum static leakage current.
Pass gates present a problem because the voltage drop across the pass gate makes it difficult to establish a valid logic signal. The problem arises when a pass gate, connected to the input of the logic gate, cannot produce a valid logic signal at the input of the logic gate. For example, if the input to the inverter in FIG. 1 is connected to an N-channel pass gate 24 as shown in FIG. 2, then the voltage at the input of the inverter can only be as high as the supply voltage less a threshold voltage drop across the N-channel pass gate 24. Given that a threshold voltage for a typical N-channel pass gate is 1 volt for a 5 volt or recharacterized 3 volt circuit, the input voltage of the inverter cannot exceed 4 volts and 2 volts, respectively. These input voltages are not valid logic signals. To turn off the P-channel transistor 26, the voltage at the input 20 to the inverter has to be above 4 volts for a 5 volt process and 2.4 volts for a recharacterized 3 volt process. There is a severe static leakage current at the output (Q) of the inverter because the input voltage is insufficient to turn the P-channel transistor 26 off while the N-channel transistor 28 is on.
There are a number of proposed solutions to this problem, but they do not solve the problem without sacrificing performance. One potential solution is illustrated in FIG. 3 and described in Section 5.2.8 in "Principles of CMOS VLSI Design: A Systems Perspective" by Neil West and Kamran Eshraghian. This circuit presents a problem because it is a pass gate network 30 consisting of many N-channel transistors connected in series. Each pass gate has an associated threshold voltage drop as described above in connection with FIG. 2. As such, the output (F(A,B)) may not produce a valid logic signal, especially for a recharacterized circuit.
To help solve the problem, a pull-up transistor 32 is connected to the pass gate as shown in FIG. 3. If the pull-up transistor 32 is small, then the pass gate network has a better pull-down transition time. However, a small pull-up transistor severely degrades the pull-up transition time. On the other hand, if the pull-up transistor 32 is larger, then the pass gate network has a better pull-up transition time but a severely degraded pull-down transition time.
The pass gate design illustrated in FIG. 4 and described in "A 3.8-ns CMOS 16.times.16-b Multiplier Using Complementary Pass-Transistor Logic" by K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu, presents an alternative approach. FIG. 4 illustrates a complementary pass gate circuit including complementary gate inputs 34, complementary drain inputs 36, an nMOS pass-transistor logic network 38, CMOS output inverters 40, 42, and a pair of pull-up transistors 44, 46. This pass gate circuit has the same drawbacks as discussed above. The switching speed of this circuit design decreases as additional pass gates are added in series. The capacitance increases with the addition of more pass gates, decreasing the speed of the circuit.
The problem posed by these pass gate circuits becomes even worse for the 3 volt recharacterized process. Even with the pull-up transistors, the output of the pass gate network can only reach 2 volts in a 3 volt recharacterized circuit. This output voltage is well below the minimum valid logic high voltage (2.4 volt for the 3 volt circuit). Therefore, the pull-up transistor requires more time to pull-up, and thus slows down the speed of the circuit.
U.S. Pat. No. 5,162,666, entitled "Transmission Gate Series Multiplexer" provides another alternative circuit design. The transmission gate multiplexer described in this patent has reduced capacitance at the output and the selection lines of the multiplexer. It therefore provides improved switching speed relative to the other designs discussed above. While a pass gate logic circuit designed according to this patent performs well when fabricated according to a 5 volt process and a 3 volt process, the pass gate logic circuit does not achieve acceptable performance when recharacterized for 3 volt operation. The 3 volt recharacterized circuit does not perform well because the threshold voltage drop across a pass gate prevents the pass gate from producing a valid logic signal at its output.
As is apparent from these prior art designs, there is a need for a pass gate logic cell design that provides improved performance, even as the number of pass gates increases. Since both 5 volt and 3 volt operation are in demand, the improved pass gate logic cell must also be able to operate well at 5 volts as well as at a recharacterized 3 volts.